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Lab Resources
- Verilog 73.2%
- Python 18.4%
- Makefile 6.1%
- Assembly 1.7%
- Tcl 0.6%
| Filename | Latest commit message | Latest commit date |
|---|---|---|
| Lab1 | ||
| Lab2-3 | ||
| Lab4 | ||
| Lab5 | ||
| Lab6-7 | ||
| Lab8 | ||
| README.md | ||
Lab Resources for HW SYN LAB
Clone this repository or download zip file of this repository and follow instructions for each lab.
Directory Structure
In each lab, there are mainly 3 directories:
src: The source directory which contains template of Verilog design of modules.sim: The directory contains Verilog files for simulation.cocotb: The python testbenches and Makefiles.