forked from Mirrors/hw-syn-lab-upstream
Lab assignments for 2110363 Hardware Synthesis Laboratory I (2024/2)
- Verilog 66.1%
- Tcl 15.8%
- Python 12.8%
- Makefile 3.7%
- Assembly 1.1%
- Other 0.5%
| Filename | Latest commit message | Latest commit date |
|---|---|---|
| Lab1 | ||
| Lab2-3 | ||
| Lab4 | ||
| Lab5 | ||
| Lab6-7 | ||
| Lab8 | ||
| Prelab | ||
| SkillTest1Prep | ||
| .gitignore | ||
| all.sh | ||
| Basys-3-Master.xdc | ||
| build.sh | ||
| README.md | ||
| upload.sh | ||
Lab Resources for HW SYN LAB
Clone this repository or download zip file of this repository and follow instructions for each lab.
Directory Structure
In each lab, there are mainly 3 directories:
src: The source directory which contains template of Verilog design of modules.sim: The directory contains Verilog files for simulation.cocotb: The python testbenches and Makefiles.